1. Field of the Invention
The present invention generally relates to a sense amplifier and bit decoder usable, for example, in electronic random access memories and, more particularly, to a sense amplifier with an integrated latch function combined with a bit decoder for memories which have extremely short access and propagation times and which may be operated in a pipelined mode to include, for example, a write-only access during a portion of a memory cycle and well as to perform other functions within the memory such as the concatenation of sense amplifier output fields read out over multiple memory operation cycles.
2. Description of the Prior Art
Electronic data processing, at its most basic level, usually involves a fetch of an instruction and/or data signal from memory, performance of an operation on or in response to that signal and storage of a resulting signal. The speed at which a data processing operation or instruction can be executed is therefore highly dependent on the cycle time required for a memory operation to retrieve and/or store a digital signal in memory. Digital signal storage can be done in many diverse media; each having characteristic properties, advantages and access times.
Static memories include a bistable memory element. Dynamic memories require refreshing since their memory elements rely on stored charge. Both static and dynamic memories typically use sense amplifiers to detect and amplify small signal voltage differences produced by the memory cells. Sense amplifier are designed to minimize noise sources: transistor parametric variations, charge sharing, signal coupling, and power supply noise.
Whether the memory is of the static or dynamic type, certain additional structure is necessary in order to access a particular memory cell, to determine its contents and to develop and deliver an output which is stable and reliably timed. Whether in the form of latches, gates inverters or other types of circuits, such structures generally perform logical functions within the memory device. In the past, such logic circuitry has been of generally the same design as would be used to perform logic functions in a processor or any other form of digital circuit. That is, the response of the circuit was generally designed to be approximately symmetrical relative to an input voltage level. Thus, when the input voltages, often including a clock signal, became relatively stable, a stable output and sufficient noise margins were generally assured and recovery from noise disturbances were possible within the same clock cycle. (These forms of logic circuit will be referred to hereinafter as static logic to more readily distinguish from so-called precharged logic circuits, occasionally referred to as dynamic logic, which follows.)
More recently, several significant advantages over static logic circuits have been realized by the development of logic circuit designs which are highly asymmetrical in response to both input voltage levels and response speed. The basic theory of the response speed improvement in such devices is that propagation time of a logic element will be minimized if the circuit can be brought to a logic state from which it may rapidly be switched to another logic state before data is applied to it. Then, when data is applied, switching of the logic state is only done when the input signal requires such a change. Thus, the circuit can be easily optimized to enhance the speed of such a transition. The establishment of the logic state before an input signal is applied is generally referred to as precharging.
Other advantages also accrue from such logic designs. Consider, for example, a CMOS inverter comprised of an N-channel FET and a P-channel FET. To obtain symmetrical response, the P-channel FET must be of approximately twice the size (and gate capacitance) of the N-channel FET. In a dynamic or precharged logic device having a comparable function, complementary transistors need not be provided with a consequent decrease in element count and gate capacitance. Moreover, the transistor used to provide or hold the precharged state may be very weak (e.g. of relatively low conductivity) and thus of reduced size.
Unfortunately, while the potential gains in speed of operation are substantial using precharged or dynamic logic, response of the circuit is more sensitive to noise and recovery from a transition triggered by noise cannot readily be accomplished within the same cycle time (e.g. a clock cycle or a memory operation cycle).
For this reason also, precharged logic circuits require meticulous tracking and analysis of effects such as noise sources, charge sharing, signal coupling, power supply considerations and the like, particularly when used in critical paths of digital signal processing circuitry. In this regard, it should be understood that digital signal processing generally involves logical operations on combinations of signals and signals of the correct logical levels must be present at the time the logical operation is carried out in order to achieve the correct result. Therefore, variations in signal level which may be encountered in normal operations of digital circuits may cause erroneous operation when applied to precharged logic circuits unless timing is carefully analyzed and controlled to assure that voltage levels will be properly recognized as the logical states they are intended to represent.
However, precharging of a circuit and the design of circuits in which precharging can be exploited are not necessarily straightforward since states of transistors may be achieved which cause transient serial conduction paths if precharge and evaluation transistors are simultaneously active. This results in excessive power consumption which may, in turn, affect response speed or pull voltage levels away from the intended logic states. Precharging can thus easily defeat the gains to be derived by design for asymmetrical circuit response and precharging, particularly where precharging proceeds in a sequence of steps. Further, providing a high impedance state of one or more transistors may increase susceptibility of the circuit to noise from any of several sources which would be especially deleterious to the operation of a precharged circuit.
It should also be noted that the above asymmetrical response speed design concept and precharging cannot reliably be used in circuits which receive signals from a circuit which is not driven solidly to logic level voltages (e.g. power supply and ground). If such a circuit is precharged and supplied with an ambiguous input voltage, the output may be in error since precharge logic circuits, by their nature, have little noise tolerance and thus may result in outputs having voltages which are even more ambiguous as well as including effects of noise sources and power supply variation (e.g. "bounce") when common-mode currents are drawn; possibly being of sufficient severity to cause erroneous operation or triggering of a precharged circuit. When such a circuit (including dynamic logic circuits) is erroneously triggered after precharge, it is virtually impossible and certainly highly impractical to provide for recovery prior to the next operation cycle.
In view of the above design considerations, it is often attractive to mix dynamic and static types of logic circuitry to optimize both the design efficiency and performance of a particular digital processor arrangement or logic directly responsive to memory output memory. For example, it is known to add a static latch to a sense amplifier to extend the time period during which a bit read from memory will be available beyond the end of a particular memory cycle.
As is known, sense amplifiers generally operate by initially bringing a bistable circuit to a balanced condition between its stable states; from which condition, the sense amplifier can be unbalanced and made to assume one of its stable states by an extremely small voltage difference. Therefore, a sense amplifier must be precharged. Precharging must be completed prior to the development of the small voltage difference (which represents the memory cell state) on the sense amplifier internal nodes. A small voltage must exist at the inputs of the sense amplifier in order for proper operation of the sense amplifier to occur.
By the same token, since precharge of the sense amplifier also balances the voltages on the output nodes, data is not available from the sense amplifier once precharging of the sense amplifier has begun. Additionally, in known designs which add a static latch to the sense amplifier, the static latch must be reset or precharged prior to a subsequent enabling of the sense amplifier. Therefore, some aspects of timing may remain critical when extremely high speed of operation is required.
It should also be understood that, at the present state of the art, substantial design effort may be expended to obtain a seemingly small percentage increase in response speed. An improvement of 10%, for example, is considered to be a very large improvement. One reason for the difficulty in obtaining larger improvements is that each design strategy, such as precharging of circuits with asymmetrical response speeds, also requires a finite amount of time to carry out and some finite time margin to reach a stable operating state of the circuit in response to such an operation. For example, if precharging does not occur sufficiently early in a memory cycle to be completed before a memory cell is accessed to couple the memory cell output to the sense amplifier, malfunction of the sense amplifier may occur because the precharge network will retard the development of a differential voltage on the sensing nodes.
Other uses of a sense amplifier within a memory device, such as multiplexing inputs thereto to provide additional operations within a single cycle can also cause an erroneous write to memory unless precautions are taken. As alluded to above, much design effort has been expended in seeking to obtain several operations within a single clock cycle. One such technique is referred to as pipelining, in which several operations, which may be of different types (such as read and write) regularly occur at different phases of the same clock cycle. For example, a memory which provides two read-write operations and one write-only operation in a single processor cycle of 15 nanoseconds is disclosed in "A 200 MHz Internal/66 MHz External 64 kB Embedded Virtual Three Port Cache SRAM" by G. Braceras et al., 1994 International Solid State Circuits Conference, ISSCC94/Session 15/Static memory for High-Bandwidth Systems/Paper FA15.3, which is hereby incorporated by reference.